1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. vr11.1, vr12 compatible synchronous rectified buck mosfet driver isl6627 the isl6627 is a high frequency mosfet driver designed to drive upper and lower power n-channel mosfets in a synchronous rectified buck converter topology. the advanced pwm protocol of isl6627 is specifically designed to work with intersil vr11.1, vr12 controllers and combined with n-channel mosfets to form a complete core-voltage regulator solution for advanced microprocessors. when isl6627 detects a psi protocol sent by an intersil vr11.1, vr12 controll er, it activates diode emulation (de) operation; otherwise, it operates in normal continuous conduction mode (ccm) pwm mode. to further enhance light load efficiency, the isl6627 enables diode emulation operation during psi mode. this allows discontinuous conduction mode (dcm) by detecting when the inductor current reaches zero and subsequently turning off the low side mosfet to prevent it from sinking current. when isl6627 detects diode braking command from the pwm, it turns off both gates and reduces overshoot in load transient situations. an advanced adaptive shoot-throug h protection is integrated to prevent both the upper and lo wer mosfets from conducting simultaneously and to minimize de ad time. the user also has the option to program the driver working in fixed propagation delay mode to optimize the regulato r efficiency. the isl6627 has a 20k ? integrated high-side gate-to-so urce resistor to prevent self turn-on due to high input bus dv/dt. related literature ? technical brief tb363 ?guidelines for hand ling and processing moisture sensitive surface mount devices (smds)? ? technical brief tb417 ?designing stable compensation networks for single phase voltage mode buck regulators? features ? intersil vr11.1 and vr12 compatible ? dual mosfet driver for synchronous rectified bridge ? advanced adaptive zero shoot-through protection ? programmable fixed deadtime for efficiency optimization ? low standby bias current ? 36v internal bootstrap diode ? bootstrap capacitor overcharge prevention ? supports high switching frequency - 4a sinking current capability - fast rise/fall times and low propagation delays ? integrated high-side gate-to-source resistor to prevent self turn-on due to high input bus dv/dt ? power rails undervoltage protection ? expandable bottom copper pad for enhanced heat sinking ? dual flat 10 ld (3x3 dfn) package - near chip-scale package footprint; improves pcb efficiency and thinner in profile ? pb-free (rohs compliant) applications ? high light load efficiency voltage regulators ? core regulators for advanced microprocessors ? high current dc/dc converters ? high frequency and high efficiency vrm and vrd en vcc pwm +5v 33.6k 28.8k boot ugate phase lgate gnd shoot- through protection/ 20k ? control logic por/ td delay programming figure 1. isl6627 block diagram september 22, 2011 fn6992.0
isl6627 2 fn6992.0 september 22, 2011 typical application circuit vcc imon vsen rgnd en_vtt vtt svdata vr_rdy rset auto cpu load vinf en_pwr_cfp isl6367 +5v vr_rdys vr_hot# isen1- isen1+ pwm1 +5v vcc pwm boot ugate phase lgate gnd isl6627 driver isen2- isen2+ pwm2 +5v vcc pwm boot ugate phase lgate gnd isl6627 driver isen6- isen6+ pwm6 +5v vcc pwm boot ugate phase lgate gnd vinf isl6596 driver svclk svalert# imons fs_drp fss_drps vinf ramp_adj +5v bts_des_tcomps +5v addr_imaxs_tmax +5v npsi_de_imax comps fbs hfcomps/dvcs hfcomp isen3-5- isen3-5+ pwm3-5 gnd gpu load vsens rgnds isens- isens+ pwms +5v vcc pwm boot ugate phase lgate gnd vinf isl6627 driver ntc: beta = 3477 tm +5v ntc vin vinf vinf isenin+ isenin- r isenin1 +5v tms +5v ntc r isenin2 bt_fdvid_tcomp psicomp fb dvc comp cfp r senin i2clk pmalert# i2data en en vctrl en
isl6627 3 fn6992.0 september 22, 2011 pin configuration isl6627 (10 ld 3x3 dfn) top view 2 3 4 1 5 9 8 7 10 6 ugate boot td pwm gnd phase en nc vcc lgate pad (gnd) functional pin descriptions pin # symbol description 1 ugate upper gate drive output. connect to gate of high-side power n-channel mosfet. 2 boot floating bootstrap supply pin for the upper gate drive. connect the bootstrap capacitor between this pin and the phase pin. the bootstrap capacitor pr ovides the charge to turn on the upper mosfet. see ?internal bootstrap device? on page 7 for guidance in choosing the capacitor value. 3 td deadtime programming pin. connect to ground or vcc via resistor to program fixed time delay from lgate fall to ugate rise or ugate fall to lgate rise. open pin se ts the adaptive mode. see table 1 for more details. 4 pwm control input for the driver. the pwm signal can enter three distinct states during operation; see ?advanced pwm protocol (patent pending)? on page 6 for further details. connect this pin to the pwm output of the controller. 5 gnd bias and reference ground. all signal s are referenced to this node. it is also the power ground return of the driver. 6 lgate lower gate drive output. connect to gate of the low-side power n-channel mosfet. 7 vcc connect to 5v bias supply. this pin supplies power to the gate drives and small-signal circuitry. place a high quality low esr ceramic capaci tor from this pin to gnd. 8ncno connection. 9 en enable input pin. connect this pin high to en able the driver and low to disable the driver. - pad epad at ground potential. soldering it directly to gnd plane is required for thermal considerations. ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # isl6627crz 6627 0 to +70 10 ld 3x3 dfn l10.3x3 ISL6627IRZ 627i -40 to +85 10 ld 3x3 dfn l10.3x3 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb- free products are msl classified at pb-free peak reflow temperat ures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl6627 . for more information on msl please see techbrief tb363 .
isl6627 4 fn6992.0 september 22, 2011 absolute maximum rating s thermal information supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 7v input voltage (v en , v pwm ). . . . . . . . . . . . . . . . . . . . . . . -0.3v to vcc + 0.3v boot voltage (v boot-gnd ) . . . . . . . . . . -0.3v to 25v (dc) or 36v (<200ns) boot to phase voltage (v boot-phase ) . . . . . . . . . . . . . . . . -0.3v to 7v (dc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 9v (<10ns) phase voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 25v (dc) . . . . . . . . . . . . . . . gnd -8v (<20ns pulse width, 10 j) to 30v (<100ns) ugate voltage. . . . . . . . . . . . . . . . . . . . . . . . . . v phase - 0.3v (dc) to v boot . . . . . . . . . . . . . . . . . . .v phase - 5v (<20ns pulse width, 10 j) to v boot lgate voltage . . . . . . . . . . . . . . . . . . . . . . . . .gnd - 0.3v (dc) to vcc + 0.3v . . . . . . . . . . . . . . . . gnd - 2.5v (<20ns pulse width, 5 j) to vcc + 0.3v ambient temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.5kv charged device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1kv latch up (tested per jesd78c; class ii, level a) . . . . . . . . . . . . . . . 100ma thermal resistance ja (c/w) jc (c/w) 10 ld 3x3 dfn package (notes 4, 5). . . . . 51 10 maximum junction temperature (plastic package) . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions ambient temperature range(ISL6627IRZ) . . . . . . . . . . . . -40c to +85c ambient temperature range (isl6627crz) . . . . . . . . . . . . .0c to +70c maximum operating junction temperature . . . . . . . . . . . . . . . . . . +125c supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 10% caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications recommended operating conditions, unless otherwise noted. boldface limits apply over the operating temperature range. parameter symbol test conditions min (note 7) typ max (note 7) units vcc supply current no load switching supply current ivcc f _pwm = 300khz, vcc = 5v, en = high 1.27 ma standby supply current ivcc vcc = 5v, pwm 0v to 2.5v transition, en = high 1.85 ma vcc = 5v, pwm 0v to 2.5v transition, en = low 1.15 ma power-on reset and enable vcc rising por threshold 3.20 3.85 4.40 v vcc falling por threshold 3.00 3.52 4.00 v vcc por hysteresis 130 300 530 mv en high threshold 1.40 1.65 1.90 v en low threshold 1.20 1.35 1.55 v pwm input (see ?timing diagram? on page 6) input current ipwm vpwm = 5v 155 a vpwm = 0v -133 a three-state lower gate falling threshold vcc = 5v 1.6 v three-state lower gate rising threshold vcc = 5v 1.1 v three-state upper gate rising threshold vcc = 5v 3.2 v three-state upper gate falling threshold vcc = 5v 2.8 v ugate rise time (note 6) t_ru v cc = 5v, 3nf load, 10% to 90% 8 ns lgate rise time (note 6) t_rl vcc = 5v, 3nf load, 10% to 90% 8 ns ugate fall time (note 6) t_fu vcc = 5v, 3nf load, 10% to 90% 8 ns lgate fall time (note 6) t fl vcc = 5v, 3nf load, 10% to 90% 4 ns ugate turn-on propagation delay (note 6) t pdhu vcc = 5v, 3nf load, adaptive 28 ns lgate turn-on propagation delay (note 6) t pdhl vcc = 5v, 3nf load, adaptive 16 ns ugate turn-off propagation delay (note 6) t pdlu vcc = 5v, 3nf load 15 ns
isl6627 5 fn6992.0 september 22, 2011 lgate turn-off propagation delay (note 6) t pdll vcc = 5v, 3nf load 14 ns minimum lgate on time at diode emulation t lg_on_dm vcc = 5v 230 330 450 ns propagation delay programming ugate fall to lgate rise time t pduflr vcc = 5v, 3nf load, 90% to 10%, short resistor from td to vcc 23 ns vcc = 5v, 3nf load, 90% to 10%, 100k resistor from td to vcc 18 ns vcc = 5v, 3nf load, 90% to 10%, 330k resistor from td to vcc 15 ns vcc = 5v, 3nf load, 90% to 10%, 910k resistor from td to vcc 7ns vcc = 5v, 3nf load, 90% to 10%, short resistor from td to gnd 18 ns lgate fall to ugate rise time t pdlfur vcc = 5v, 3nf load, 90% to 10%, short resistor from td to gnd 40 ns vcc = 5v, 3nf load, 90% to 10%, 100k resistor from td to gnd 25 ns vcc = 5v, 3nf load, 90% to 10%, 360k resistor from td to gnd 17 ns vcc = 5v, 3nf load, 90% to 10%, short resistor from td to vcc 27 ns output (note 6) upper drive source current i_u_source vcc = 5v, 3nf load 2 a upper drive source impedance r_u_source 20ma source current 1 upper drive sink current i_u_sink vcc = 5v, 3nf load 2 a upper drive sink impedance r_u_sink 20ma sink current 1 lower drive source current i_l_source vcc = 5v, 3nf load 2 a lower drive source impedance r_l_source 20ma source current 1 lower drive sink current i_l_sink vcc = 5v, 3nf load 4 a lower drive sink impedance r_l_sink 20ma sink current 0.4 notes: 6. limits established by characterization and are not production tested. 7. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits established by characterization and are not production tested. electrical specifications recommended operating conditions, unless otherwise noted. boldface limits apply over the operating temperature range. (continued) parameter symbol test conditions min (note 7) typ max (note 7) units
isl6627 6 fn6992.0 september 22, 2011 operation and adaptive shoot-through protection designed for high speed switching, the isl6627 mosfet driver controls both high-side and low- side n-channel fets from one externally-provided pwm signal. a rising transition on pwm initiates the turn-off of the lower mosfet (see ?timing diagram?). after a short propagation delay [t pdll ], the lower gate begins to fall. typical fall times [t fl ] are provided in the ? electrical specifications? on page 4. adaptive shoot-through circuitry monitors the lgate voltage and turns on the upper gate following a short delay time [t pdhu ] after the lgate voltage drops below ~1v. the user also has the option to program the propagation delay as descri bed in ?deadtime programming? on page 6. the upper gate drive then begins to rise [t ru ] and the upper mosfet turns on. a falling transition on pwm indicates the turn-off of the upper mosfet and the turn-on of the lo wer mosfet. a short propagation delay [t pdlu ] is encountered before the upper gate begins to fall [t fu ]. the adaptive shoot-through circuitry monitors the ugate- phase voltage and turns on the lower mosfet a short delay time [t pdhl ], after the upper mosfet?s gate voltage drops below 1v. the lower gate then rises [t rl ], turning on the lower mosfet. these methods prevent both the lower and upper mosfets from conducting simultaneously (shoot -through), while adapting the dead time to the gate charge characteristics of the mosfets being used. the user also has the opti on to program the propagation delay as described in ?deadt ime programming? on page 6. this driver is optimized for voltage regulators with a large step down ratio. the lower mosfet is usually sized larger compared to the upper mosfet because the lower mosfet conducts for a longer time during a switching period. the lower gate driver is therefore sized much larger to m eet this application requirement. the 0.4 on-resistance and 4a sink cu rrent capability enable the lower gate driver to absorb the charge injected into the lower gate through the drain-to-gate capacito r of the lower mosfet and help prevent shoot through caused by the self turn-on of the lower mosfet due to high dv/dt of the switching node. advanced pwm protoc ol (patent pending) the advanced pwm protocol of isl6627 is specifically designed to work with intersil vr11.1 and vr12 controllers. when isl6627 detects a psi# protocol sent by an intersil vr11.1/vr12 controller, it turns on diode emulation operation; otherwise, it remains in normal ccm pwm mode. note that for a pwm low to tri-level (2.5v) transition, the lgate will not turn off until the its diode emulation minimum on-time of 330ns (typically) passes. diode emulation diode emulation allows for high er converter efficiency under light-load situations. with diod e emulation active, the isl6627 detects the zero current crossing of the output inductor and turns off lgate, preventing the low si de mosfet from sinking current and ensuring discontinuous conduc tion mode (dcm) is achieved. in dcm mode, lgate has a minimum on-t ime of 330ns (typically). deadtime programming the part provides the user with the option to program either of the two gate propagation delays (as defined in figure 3) in order to optimize the deadtime and maximize the efficiency of the circuit. tying the td pin to either gnd or vcc through a specified-value resistor leads the driver to operate in fixed gate propagation delay mode. leaving the td pin floating results in the driver operating in adaptive deadtime mode. refer to table 1 for typical programming resistor value opti ons. propagation delay has a typical tolerance of 30%. as ac tual deadtime depends on fet switching transition characterist ics, while operating in fixed propagation delay mode, the user needs to monitor the gate transitions under worst-case operating conditions and use appropriate design margin to prevent eventual shoot-through due to insufficient dead time. figure 2. timing diagram pwm ugate lgate t fl t pdhu t pdll t rl t tsshd t pdts t pdts 1.6v isl6627 7 fn6992.0 september 22, 2011 power-on reset (por) function vcc voltage level is monitored at all times. once the vcc voltage exceeds 3.85v (typically), operatio n of the driver is enabled and the pwm input signal takes control of the gate drivers. if vcc drops below the falling threshold of 3.52v (typically), operation of the driver is disabled. internal bootstrap device isl6627 features an internal bootstrap schottky diode. simply adding an external capacitor across the boot and phase pins completes the bootstrap circuit. the bootstrap function is also designed to prevent the bootstrap capacitor from overcharging due to the large negative swing at the trailing-edge of the phase node excursion. this reduces the potential for overstressing the upper driver. the bootstrap capacitor must have a voltage rating above the maximum vcc voltage. its capacitance value can be estimated from equation 1: where q g1 is the amount of gate ch arge per upper mosfet at v gs1 gate-source voltage and n q1 is the number of control (upper) mosfets. the v boot_cap term is defined as the allowable droop in the rail of the upper gate drive. select results are exemplified in figure 4. power dissipation package power dissipation is main ly a function of the switching frequency (f sw ), the output drive impedance, the layout resistance, the selected mosfet?s internal gate resistance and its total gate charge (q g ). calculating the power dissipation in the driver for a desired application is cr itical to ensure safe operation. exceeding the maximum allowable power dissipation level may push the ic beyond the maximum recommended operating junction temperature. the dfn pack age is more suitable for high frequency applications. see ?layou t considerations? on page 8 for thermal impedance improvement suggestions. the total driver power loss, essentially mosfets? gate charge and driver internal circuitry losses, can be estimated using equations 2 and 3, respectively. where the gate charge (q g1 and q g2 ) is defined at a particular gate to source voltage (v gs1 and v gs2 ) in the corresponding mosfet datasheet; i q is the driver?s total quiescent current with no load at both drive outputs; n q1 and n q2 are number of upper and lower mosfets, respectively; uvcc and lvcc are the drive voltages for both upper and lower fets, respectively. the i q* vcc product is the bias power of the driver without a load. table 1. typical delay programming resistor value resistor from td to vcc (k ) resistor from td to gnd (k ) lg fall to ug rise delay (ns) ug fall to lg rise delay (ns) short - 27 23 100 - 27 18 330 - 27 15 910 - 27 7 -short4018 - 100 25 18 - 360 17 18 floating floating adaptive adaptive figure 3. programmable propagation delay illustration pwm ug lg lg fall to ug rise propagation delay ug fall to lg rise propagation delay c boot_cap q gate v boot_cap --------------------------------- q gate q g1 vcc ? v gs1 --------------------------- n q1 ? = (eq. 1) 50nc 20nc figure 4. bootstrap capa citance vs boot ripple voltage v boot_cap (v) c boot_cap ( f) 1.6 1.4 1.2 1. 0.8 0.6 0.4 0.2 0.0 0.3 0.0 0.1 0.2 0.4 0.5 0.6 0.9 0.7 0.8 1.0 q gate = 100nc p qg_tot p qg_q1 p qg_q2 i q vcc ? ++ = (eq. 2) p qg_q1 q g1 uvcc 2 ? v gs1 ---------------------------------- - f sw ? n q1 ? = p qg_q2 q g2 lvcc 2 ? v gs2 ---------------------------------- f sw ? n q2 ? = i dr q g1 uvcc n q1 ? ? v gs1 ------------------------------------------------ q g2 lvcc n q2 ? ? v gs2 ----------------------------------------------- - + ?? ?? ?? f sw i q + ? = (eq. 3)
isl6627 8 fn6992.0 september 22, 2011 the total gate drive power loss es are dissipated among the resistive components along the transition path, as outlined in equation 4. the drive resistance dissipates a portion of the total gate drive power losses, the rest will be dissipated by the external gate resistors (r g1 and r g2 ) and the internal gate resistors (r gi1 and r gi2 ) of mosfets. figures 5 and 6 show the typical upper and lower gate drives turn-on current paths. application information mosfet and driver selection the parasitic inductances of the pcb and of the power devices? packaging (both upper and lowe r mosfets) can cause serious ringing, exceeding absolute maximum rating of the devices. the negative ringing at the edges of the phase node could increase the bootstrap capacitor voltage through the internal bootstrap diode, and in some cases, it may overstress the upper mosfet driver. careful layout, proper selection of mosfets and packaging, as well as the driver can minimize such unwanted stress. layout considerations a good layout helps reduce the ringing on the switching (phase) node and significantly lower the stress applied to the mosfets as well as the driver. the following advice is meant to lead to an optimized layout: ? keep decoupling circuit loops (vcc-gnd and boot-phase) as short as possible. ? minimize trace inductance, especially on low-impedance lines. all power traces (ugate, phase, lgate, gnd, vcc) should be short and wide, as much as possible. ? minimize the inductance of the phase node. ideally, the source of the upper and the drai n of the lower mosfet should be as close as thermally allowable. ? minimize the current loop of the output and input power trains. short the source connection of the lower mosfet to ground as close to the transistor pin as feasible. input capacitors (especially ceramic decoupling) should be placed as close to the drain of upper and source of lower mosfets as possible. in addition, connecting the thermal pad of the dfn package to the power ground through one or several vias is recommended for high switching frequency, high current applications. this is to improve heat dissipation and allow the part to achieve its full thermal potential. upper mosfet self turn-on effects at startup should the driver have insufficient bias voltage applied, its outputs are floating. if the input bus is energized at a high dv/dt rate while the driver outputs are floating, due to self-coupling via the internal c gd of the mosfet, the gate of the upper mosfet could momentarily rise up to a level greater than the threshold voltage of the device, potentially turning on the upper switch. therefore, if such a situation could conceivably be encountered, it is a common practice to place a resistor (r ugph ) across the gate and source of the upper mosfet to suppress the miller coupling effect. the value of the resistor depends mainly on the input voltage?s rate of rise, the c gd /c gs ratio, as well as the gate-source threshold of the upper mosfet. a higher dv/dt, a lower c gd /c gs ratio, and a lower gate-source threshold upper fet will require a smaller resistor to diminish the effect of the internal capacitive coupling. for most applications, the integrated 20k resistor is sufficient, not measurably affecting normal performance and efficiency. the coupling effect can be roughly estimated with equation 5, which assumes a fixed linear input ramp and neglects the clamping effect of the body di ode of the upper drive and the bootstrap capacitor. other parasitic components, such as lead inductances and pcb capacitances are also not taken into account. figure 7 provides a visual reference for this phenomenon and its potential solution. figure 5. typical upper-gate drive turn-on path figure 6. typical lower-gate drive turn-on path p dr p dr_up p dr_low i q vcc ? ++ = (eq. 4) p dr_up r hi1 r hi1 r ext1 + ----------------------------------- r lo1 r lo1 r ext1 + ------------------------------------ - + ?? ?? ?? p qg_q1 2 ------------------- ? = p dr_low r hi2 r hi2 r ext2 + ----------------------------------- r lo2 r lo2 r ext2 + ------------------------------------ - + ?? ?? ?? p qg_q2 2 ------------------- ? = r ext1 r g1 r gi1 n q1 ------------ + = r ext2 r g2 r gi2 n q2 ------------ + = q1 d s g r gi1 r g1 boot r hi1 c ds c gs c gd r lo1 phase vcc vcc q2 d s g r gi2 r g2 r hi2 c ds c gs c gd r lo2 v gs_miller dv dt ------ rc rss 1e v ? ds dv dt ------ rc ? iss ? ------------------------------- ? ?? ?? ?? ?? ?? ?? ?? = rr ugph r gi + = c rss c gd = c iss c gd c gs + = (eq. 5)
isl6627 9 fn6992.0 september 22, 2011 general powerpad design considerations figure 8 shows the recommended use of vias on the thermal pad to remove heat from the ic. this typical array populates the thermal pad footprint with vias spaced three times the radius distance from the center of each via. small via size is advisable, but not to the extent that sold er reflow becomes difficult. all vias should be connected to the pad potential, with low thermal resistance for efficient heat transfer. complete connection of the plated-through ho le to each plane is important. it is not recommended to use ?thermal relief? patterns to connect the vias. figure 7. gate to source resistor to reduce upper mosfet miller coupling vin q upper d s g r gi r ugph boot du c ds c gs c gd dl phase vcc isl6627 c boot ugate figure 8. pcb via pattern
isl6627 10 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6992.0 september 22, 2011 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl6627 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.com/reports/sear revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 9/22/11 fn6992.0 initial release.
isl6627 11 fn6992.0 september 22, 2011 package outline drawing l10.3x3 10 lead dual flat package (dfn) rev 6, 09/09 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.18mm and 0.30mm from the terminal tip. lead width applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view (4x) 0.10 index area pin 1 pin #1 index area c seating plane base plane 0.08 see detail "x" c c 5 6 6 a b 0.10 c 1 package 1.00 0.20 8x 0.50 2.00 3.00 (10x 0.23) (8x 0.50) 2.00 1.60 (10 x 0.55) 3.00 0.05 0.20 ref 10 x 0.23 10x 0.35 1.60 outline max (4x) 0.10 ab 4 c m 0.415 0.23 0.35 0.200 2 4
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